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| Advance Information PE42672 DIE SP7T UltraCMOSTM 2.75 V Switch 100 - 3000 MHz, +68 dBM IIP3 Figure 1. Functional Diagram Features * Dedicated TX1 port for WCDMA, TX2 * WCDMA TX1 RX1 * GSM/EDGE TX2 RX2 * * * GSM/EDGE TX3 RX3 RX4 CMOS Control/Driver and ESD V1 V2 V3 * * * and TX3 ports for GSM/EDGE Three pin CMOS logic control with integral decoder/driver Exceptional harmonic performance: 2fo = -84 dBc and 3fo = -77 dBc Low TX insertion loss: 0.50 dB at 900 MHz, 0.70 dB at 1900 MHz TX - RX Isolation of 44 dB at 900 MHz, 38 dB at 1900 MHz 1500 V HBM ESD tolerance all ports +68 dBm IIP3 -111 dBm IMD3 No blocking capacitors required Product Description Figure 2. Die Top View* The PE42672 is a HaRPTM-enhanced SP7T RF Switch developed on the UltraCMOSTM process technology. It addresses the specific design needs of the Quad-Band GSM Handset Antenna Switch Module Market for use in GSM/EDGE/PCS/DCS/WCDMA handsets. The switch is comprised of three TX ports and four RX ports. TX1 is designed for WCDMA and TX2 and TX3 are designed for GSM/ EDGE. The four symmetric RX ports can be used for GSM/EDGE/PCS RX. On-chip CMOS decoder logic facilitates three-pin low voltage CMOS control, while high ESD tolerance of 1500 V at all ports, no blocking capacitor requirements, and on-chip SAW filter overvoltage protection devices make this the ultimate in integration and ruggedness. Peregrine's HaRPTM technology enhancements deliver high linearity and exceptional harmonics performance. It is an innovative feature of the UltraCMOSTM process, providing performance superior to GaAs with the economy and integration of conventional CMOS. (c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 4 TX1 ANT RX1 GND GND TX2 1206 m RX2 GND RX3 GND RX4 GND GND TX3 GND GND VDD V3 GN V2 V1 GND 1006 m * Dimensions shown are drawn die size. Document No. 70-0197-01 www.psemi.com Contact sales@psemi.com for full version of datasheet PE42672 Advance Information Table 1. Target Electrical Specifications @ 25 C, VDD = 2.75 V Parameter TX - Ant (850 / 900) TX - Ant (1800 / 1900) TX - Ant ( 2200 UMTS ) RX - Ant (850 / 900) RX - Ant (1800 / 1900) Port under test in on state TX - RX (850 / 900) TX - RX (1800 / 1900) TX - TX (850 / 900) TX - TX (1800 / 1900) TX1 - RX (1900 / 2200) TX 850 / 900 MHz, +35 dBm output power, 50 TX 1800 / 1900 MHz, +33 dBm output power, 50 TX 850 / 900 MHz, +35 dBm output power, 50 TX 1800 / 1900 MHz, +33 dBm output power, 50 Condition Typ 0.5 0.7 0.8 0.8 1.0 20 44 38 29 23 37 -84 -80 -77 -73 -111 Units dB dB dB dB dB dB dB dB dB dB dB dBc dBc dBc dBc dBm Insertion loss1 Return Loss Isolation 2nd Harmonic 3rd Harmonic IMD3 distortion at 2.14 GHz TX1 Measured at 2.14 GHz at Ant port, input +20 dBm CW signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz Note: 1. Insertion loss specified with optimal impedance matching. Table 2. Operating Ranges Parameter Temperature range VDD Supply Voltage IDD Power Supply Current (VDD = 2.75 V) TX input power2 (VSWR 3:1) RX input power (VSWR =1:1) 2 Table 3. Absolute Maximum Ratings Min -40 2.65 2.75 13 Typ Max +85 2.85 50 +35 +20 1.4 0.4 Units C V A PIN(50 ) dBm dBm V V VESD ESD Voltage at ANT Port (IEC 61000-4-2) 1700 V Symbol VDD VI TST Parameter/Conditions Power supply voltage Voltage on any input Storage temperature range TX input power (50 ) RX input power (50 ) 3,4 3,4 3,4 Symbol TOP VDD IDD PIN PIN VIH VIL Min -0.3 -0.3 -65 Max 4.0 VDD+ 0.3 +150 +38 Units V V C dBm +23 +35 1500 dBm V PIN (:1) TX input power (VSWR = :1) ESD Voltage (HBM, MIL_STD 883 Method 3015.7) Control Voltage High Control Voltage Low Note: 2. Assumes RF input period of 4620 s and duty cycle of 50%. Note: 3. Assumes RF input period of 4620 s and duty cycle of 50%. 4. V DD within operating range specified in Table 2. Part performance is not guaranteed under these conditions. Exposure to absolute maximum conditions for extended periods of time may adversely affect reliability. Stresses in excess of absolute maximum ratings may cause permanent damage. (c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 4 Document No. 70-0197-01 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet PE42672 Advance Information Table 4. Pin Descriptions Pin No. 1 2 6 Figure 3. Pad Configuration (Top View) ANT TX1 Pin Name ANT TX1 GND TX2 GND TX3 GND GND VDD V3 GND V2 V1 GND GND RX4 GND RX3 GND RX2 GND RX1 Description RF Common - Antenna 2 1 22 21 RX1 GND RX2 GND RX3 GND RX4 GND RF I/O - TX1 Ground (Requires two bond wires) RF I/O - TX2 Ground RF I/O - TX3 Ground Ground Supply Switch control input, CMOS logic level Ground Switch control input, CMOS logic level Switch control input, CMOS logic level Ground Ground RF I/O - RX4 Ground RF I/O - RX3 Ground RF I/O - RX2 Ground RF I/O - RX1 GND 6 8 9 10 11 12 13 35 46 55 65 75 85 9 10 11 5 GND TX2 GND TX3 GND 3 4 20 19 5 6 PE42672 Die 18 17 16 15 7 14 V3 GND V2 V1 12 13 14 5 Table 5. Truth Table Path RX1 - ANT RX2 - ANT RX3 - ANT RX4 - ANT TX1 - ANT TX2 - ANT TX3 - ANT All Off V1 0 1 0 1 0 1 0 1 V2 0 0 1 1 0 0 1 1 V3 0 0 0 0 1 1 1 1 155 166 17 18 19 20 21 5 6 5 6 5 Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. 226 Notes: 5. Bond wires should be physically short and connected to ground plane for best performance. 6. Blocking capacitors needed only when non-zero DC voltage present. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Table 6. Ordering Information Order Code 42672-90 42672-99 42672-00 Description PE42672-DIE-D PE42672-DIE-400G PE42672-DIE-1H Package Film Frame Waffle Pack Evaluation Kit Shipping Method Wafer (Gross Die / Wafer Quantity) 400 Dice / Waffle Pack 1/ box Document No. 70-0197-01 www.psemi.com Contact sales@psemi.com for full version of datasheet (c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 4 GND VDD PE42672 Advance Information Sales Offices The Americas Peregrine Semiconductor Corp. 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 North Asia Pacific Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor Europe Commercial Products: Batiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 Space and Defense Products: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 South Asia Pacific Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). (c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 4 Document No. 70-0197-01 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet |
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